/*
 * RT-Thread Secure
 *
 * Copyright (c) 2021, Shanghai Real-Thread Electronic Technology Co., Ltd.
 *
 * All rights reserved.
 */
#ifndef __RK3568_CLK_H__
#define __RK3568_CLK_H__

#define PMU_CRU_BASE_ADDR       (0xFDD00000)
#define PMU_SCRU_BASE_ADDR      (0xFDD30000)
#define CRU_BASE_ADDR           (0xFDD20000)
#define SCRU_BASE_ADDR          (0xFDD10000)

#define CRU_MODE                0x00C0
#define PMU_CRU_MODE            0x0080

#define RK3568_PLL_CON(x)		((x) * 0x4)
#define RK3568_MODE_CON0		0xc0
#define RK3568_MISC_CON0		0xc4
#define RK3568_MISC_CON1		0xc8
#define RK3568_MISC_CON2		0xcc
#define RK3568_GLB_CNT_TH		0xd0
#define RK3568_GLB_SRST_FST		0xd4
#define RK3568_GLB_SRST_SND		0xd8
#define RK3568_GLB_RST_CON		0xdc
#define RK3568_GLB_RST_ST		0xe0
#define RK3568_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
#define RK3568_CLKGATE_CON(x)		((x) * 0x4 + 0x300)
#define RK3568_SOFTRST_CON(x)		((x) * 0x4 + 0x400)
#define RK3568_SDMMC0_CON0		0x580
#define RK3568_SDMMC0_CON1		0x584
#define RK3568_SDMMC1_CON0		0x588
#define RK3568_SDMMC1_CON1		0x58c
#define RK3568_SDMMC2_CON0		0x590
#define RK3568_SDMMC2_CON1		0x594
#define RK3568_EMMC_CON0		0x598
#define RK3568_EMMC_CON1		0x59c

#define RK3568_PMU_PLL_CON(x)		RK3568_PLL_CON(x)
#define RK3568_PMU_MODE_CON0		0x80
#define RK3568_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x100)
#define RK3568_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)
#define RK3568_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)

/* CRU_PLL_Mode */
#define CRU_PLL_MODE_MASK		    0x3
#define CRU_PLL_MODE_SLOW		    0x0
#define CRU_PLL_MODE_NORM		    0x1
#define CRU_PLL_MODE_DEEP		    0x2

/* CRU_PLL_MASK */
#define CRU_PLL_PD_MASK             0x6000
#define CRU_PLL_POSTDIV1_MASK       0x7000
#define CRU_PLL_FBDIV_MASK          0xFFF
#define CRU_PLL_REFDIV_MASK         0x3F
#define CRU_PLL_POSTDIV2_MASK       0x1C0
#define CRU_PLL_FRAC_MASK           0xFFFFFF
#define CRU_PLL_LOCK_STATUS_MASK    0x400
#define CRU_PLL_DSMPD_MASK          0x1000

/* CRU_PLL_SHIFT */
#define CRU_PLL_POSTDIV1_SHIFT      12
#define CRU_PLL_FBDIV_SHIFT         0
#define CRU_PLL_POSTDIV2_SHIFT      6
#define CRU_PLL_REFDIV_SHIFT        0
#define CRU_PLL_DSMPD_SHIFT         12
#define CRU_PLL_FRAC_SHIFT          0

#endif